Re-Defining the Tournament Predictor for Embedded Systems

Looking at trends in recent publications on computer architecture we find that there has been a steep decline in the number of published works relating to branch prediction. Further inspection reveals that while older trends include development of new predictor designs [12][15][8][10], more modern trends have been favoring the consumption of larger history and storage to attain better hit rates [4][3][14][11]. The few new developments in new designs of branch predictors, excluding neural predictors[5][6], generally involve slight modifications to the baseline predictors (bimodal, gshare, and tournament predictors) and can be seen in works such as [9][1][2][7][13]. In this work we present the need for application specific branch prediction in power constrained embedded systems, along with an example demonstrating the performance gains and power reduction for a fraction of the cost paid in advanced predictors mentioned above. 1 Evaluation of Branch